View MX29F004BQI-70_1938334.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

1 mx29f004t/b 4m-bit [512kx8] cmos flash memory features ? 524,288 x 8 only ? single power supply operation - 5.0v only operation for read, erase and program op- eration ? fast access time: 70/90/120ns ? low power consumption - 30ma maximum active current (5mhz) - 1ua typical standby current ? command register architecture - byte programming (7us typical) - sector erase (sector structure:16kb/8kb/8kb/32kb and 64kbx7) ? auto erase (chip & sector) and auto program - automatically erase any combination of sectors with erase suspend capability. - automatically program and verify data at specified address during erase and programming, while maintaining maxi- mum eprom compatibility. mxic flash technology reliably stores memory contents even after 100,000 erase and program cycles. the mxic cell is designed to optimize the erase and programming mechanisms. in addition, the combination of advanced tunnel oxide processing and low internal electric fields for erase and program operations produces reliable cycling. the mx29f004t/b uses a 5.0v 10% vcc supply to perform the high reliability erase and auto program/erase algorithms. the highest degree of latch-up protection is achieved with mxic's proprietary non-epi process. latch-up protection is proved for stresses up to 100 milliamps on address and data pin from -1v to vcc + 1v. general description the mx29f004t/b is a 4-mega bit flash memory orga- nized as 512k bytes of 8 bits. mxic's flash memories offer the most cost-effective and reliable read/write non- volatile random access memory. the mx29f004t/b is packaged in 32-pin plcc, tsop, pdip. it is designed to be reprogrammed and erased in system or in stan- dard eprom programmers. the standard mx29f004t/b offers access time as fast as 70ns, allowing operation of high-speed microproces- sors without wait states. to eliminate bus contention, the mx29f004t/b has separate chip enable (ce) and output enable (oe) controls. mxic's flash memories augment eprom functionality with in-circuit electrical erasure and programming. the mx29f004t/b uses a command register to manage this functionality. the command register allows for 100% ttl level control inputs and fixed power supply levels ? erase suspend/erase resume - suspends an erase operation to read data from, or program data to, another sector that is not being erased, then resumes the erase. ? status reply - data polling & toggle bit for detection of program and erase cycle completion. ? chip protect/unprotect for 5v only system or 5v/12v system. ? 100,000 minimum erase/program cycles ? latch-up protected to 100ma from -1v to vcc+1v ? low vcc write inhibit is equal to or less than 3.2v ? package type: - 32-pin plcc, tsop or pdip ? compatibility with jedec standard - pinout and software compatible with single-power supply flash ? 20 years data retention p/n:pm0554 rev. 1.6, jul. 18, 2002
2 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 pin configurations 32 plcc 32 tsop (standard type) (8mm x 20mm) symbol pin name a0~a18 address input q0~q7 data input/output ce chip enable input we write enable input oe output enable input gnd ground pin vcc +5.0v single power supply pin description 32 pdip mx29f004t/b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a16 a15 a12 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 vcc we a17 a14 a13 a8 a9 a11 oe a10 ce q7 q6 q5 q4 q3 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe a10 ce q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd q3 q4 q5 q6 a12 a15 a16 a18 vcc we a17 mx29f004t/b a11 a9 a8 a13 a14 a17 we vcc a18 a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe a10 ce q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx29f004t/b
3 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 sector size address range (in hexadecimal) sector a18 a17 a16 a15 a14 a13 (kbytes) (x8) address range sa0000x xx 64 00000h-0ffffh sa1001x xx 64 10000h-1ffffh sa2010x xx 64 20000h-2ffffh sa3011x xx 64 30000h-3ffffh sa4100x xx 64 40000h-4ffffh sa5101x xx 64 50000h-5ffffh sa6110x xx 64 60000h-6ffffh sa71110 xx 32 70000h-77fffh sa81111 00 8 78000h-79fffh sa91111 01 8 7a000h-7bfffh sa10 1111 1x 16 7c000h-7ffffh sector structure mx29f004t top boot sector address table sector size address range (in hexadecimal) sector a18 a17 a16 a15 a14 a13 (kbytes) (x8) address range sa00000 0x 16 00000h-03fffh sa10000 10 8 04000h-05fffh sa20000 11 8 06000h-07fffh sa30001 xx 32 08000h-0ffffh sa4001x xx 64 10000h-1ffffh sa5010x xx 64 20000h-2ffffh sa6011x xx 64 30000h-3ffffh sa7100x xx 64 40000h-4ffffh sa8101x xx 64 50000h-5ffffh sa9110x xx 64 60000h-6ffffh sa10 111x xx 64 70000h-7ffffh mx29f004b bottom boot sector address table
4 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 block diagram control input logic program/erase high voltage write s tat e machine (wsm) s tat e register mx29f004t/b flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-a18 ce oe we
5 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 automatic programming the mx29f004t/b is byte programmable using the au- tomatic programming algorithm. the automatic pro- gramming algorithm makes the external system do not need to have time out sequence nor to verify the data programmed. the typical chip programming time at room temperature of the mx29f004t/b is less than 4 sec- onds. automatic chip erase the entire chip is bulk erased using 10 ms erase pulses according to mxic's automatic chip erase algorithm. typical erasure at room temperature is accomplished in less than 4 second. the automatic erase algorithm automatically programs the entire array prior to electri- cal erase. the timing and verification of electrical erase are controlled internally within the device. automatic sector erase the mx29f004t/b is sector(s) erasable using mxic's auto sector erase algorithm. sector erase modes allow sectors of the array to be erased in one erase cycle. the automatic sector erase algorithm automatically programs the specified sector(s) prior to electrical erase. the timing and verification of electrical erase are con- trolled internally within the device. automatic programming algorithm mxic's automatic programming algorithm requires the user to only write program set-up commands (including 2 unlock write cycle and a0h) and a program command (program data and address). the device automatically times the programming pulse width, provides the pro- gram verification, and counts the number of sequences. a status bit similar to data polling and a status bit tog- gling between consecutive read cycles, provide feed- back to the user as to the status of the programming operation. automatic erase algorithm mxic's automatic erase algorithm requires the user to write commands to the command register using stan- dard microprocessor write timings. the device will auto- matically pre-program and verification the entire array. then the device automatically times the erase pulse width, provides the erase verify, and counts the number of sequences. a status bit toggling between consecu- tive read cycles provides feedback to the user as to the status of the programming operation. register contents serve as inputs to an internal state- machine which controls the erase and programming cir- cuitry. during write cycles, the command register inter- nally latches address and data needed for the program- ming and erase operations. during a system write cycle, addresses are latched on the falling edge of we or ce, whichever happens later, and data are latched on the rising edge of we or ce, whichever happens first. mxic's flash technology combines years of eprom experience to produce the highest levels of quality, reli- ability, and cost effectiveness. the mx29f004t/b elec- trically erases all bits simultaneously using fowler- tun- neling. the bytes are programmed by using the eprom programming mechanism of hot electron injection. during a program cycle, the state-machine will control the program sequences and command register will not respond to any command set. during a sector erase cycle, the command register will only respond to erase suspend command. after erase suspend is completed, the device stays in read mode. after the state machine has completed its task, it will allow the command regis- ter to respond to its full command set.
6 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 first bus second bus third bus fourth bus fifth bus sixth bus command bus cycle cycle cycle cycle cycle cycle cycle addr data addr data addr data addr data addr data addr data reset 1 xxxh f0h read 1 ra rd read silicon id 4 555h aah 2aah 55h 555h 90h adi ddi chip protect verify 4 555h aah 2aah 55h 555h 90h sa 00h x02 01h program 4 555h aah 2aah 55h 555h a0h pa pd chip erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 10h sector erase 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h sa 30h sector erase suspend 1 xxxh b0h sector erase resume 1 xxxh 30h unlock for chip 6 555h aah 2aah 55h 555h 80h 555h aah 2aah 55h 555h 20h protect/unprotect table1. software command definitions note: 1. adi = address of device identifier; a1=0, a0 = 0 for manufacture code,a1=0, a0 =1 for device code a2~a18=do not care. (refer to table 3) ddi = data of device identifier : c2h for manufacture code, 45h/46h for device code. x = x can be vil or vih ra=address of memory location to be read. rd=data to be read at location ra. 2. pa = address of memory location to be programmed. pd = data to be programmed at location pa. sa = address to the sector to be erased. 3. the system should generate the following address patterns: 555h or 2aah to address a10~a0. address bit a11~a18=x=don't care for all address commands except for program address (pa) and sector address (sa). write sequence may be initiated with a11~a18 in either state. 4. for chip protect verify operation :if read out data is 01h, it means the chip has been protected. if read out data is 00h, i t means the chip is still not being protected. command definitions device operations are selected by writing specific ad- dress and data sequences into the command register. writing incorrect address and data values or writing them in the improper sequence will reset the device to the read mode. table 1 defines the valid register command sequences. note that the erase suspend (b0h) and erase resume (30h) commands are valid only while the sector erase operation is in progress. either of the two reset command sequences will reset the device (when applicable).
7 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 mode pins ce oe we a0 a1 a6 a9 q0 ~ q7 read silicon id l l h l l x v id (2) c2h manufacturer code (1) read silicon id l l h h l x v id (2) 45h/46h device code (1) read l l h a0 a1 a6 a9 d out standby h x x x x x x high z output disable l h h x x x x high z write l h l a0 a1 a6 a9 d in (3) chip protect with 12v l v id (2) l x x l v id (2) x system (6) chip unprotect with 12v l v id (2) l x x h v id (2) x system (6) verify chip protect l l h x h x v id (2) code (5) with 12v system chip protect without 12v l h l x x l h x system (6) chip unprotect without 12v l h l x x h h x system (6) verify chip protect/unprotect l l h x h x h code (5) without 12v system (7) reset x x x x x x x high z table 2. mx29f004t/b bus operation notes: 1. manufacturer and device codes may also be accessed via a command register write sequence. refer to table 1. 2. vid is the silicon-id-read high voltage, 11.5v to 12.5v. 3. refer to table 1 for valid data-in during a write operation. 4. x can be vil or vih. 5. code=00h means unprotected. code=01h means protected. 6. refer to chip protect/unprotect algorithm and waveform. must issue "unlock for chip protect/unprotect" command before "chip protect/unprotect without 12v system" command. 7. the "verify chip protect/unprotect without 12v system" is only following "chip protect/unprotect without 12v system" command.
8 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 read/reset command the read or reset operation is initiated by writing the read/ reset command sequence into the command register. microprocessor read cycles retrieve array data. the de- vice remains enabled for reads until the command regis- ter contents are altered. if program-fail or erase-fail happen, the write of f0h will reset the device to abort the operation. a valid com- mand must then be written to place the device in the desired state. silicon-id-read command flash memories are intended for use in applications where the local cpu alters memory contents. as such, manu- facturer and device codes must be accessible while the device resides in the target system. prom program- mers typically access signature codes by raising a9 to a high voltage. however, multiplexing high voltage onto address lines is not generally desired system design prac- tice. the mx29f004t/b contains a silicon-id-read operation to supplement traditional prom programming method- ology. the operation is initiated by writing the read sili- con id command sequence into the command register. following the command write, a read cycle with a1=vil,a0=vil retrieves the manufacturer code of c2h. a read cycle with a1=vil, a0=vih returns the device code of 45h/46h for mx29f004t/b. set-up automatic chip/sector erase chip erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the "set-up" command 80h. two more "unlock" write cy- cles are then followed by the chip erase command 10h. the automatic chip erase does not require the device to be entirely pre-programmed prior to executing the au- tomatic chip erase. upon executing the automatic chip erase, the device will automatically program and verify the entire memory for an all-zero data pattern. when the device is automatically verified to contain an all-zero pattern, a self-timed chip erase and verify begin. the erase and verify operations are completed when the data on q7 is "1" at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic chip erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). if the erase operation was unsuccessful, the data on q5 is "1" (see table 4), indicating the erase operation exceed internal timing limit. the automatic erase begins on the rising edge of the last we or ce, whicheven happens first pulse in the command sequence and terminates when the data on q7 is "1" and the data on q6 stops toggling for two con- secutive read cycles, at which time the device returns to the read mode. pins a0 a1 q7 q6 q5 q4 q3 q2 q1 q0 code (hex) manufacture code vil vil 1 1 0 0 0 0 1 0 c2h device code for mx29f004t vih vil 0 1 0 0 0 1 0 1 45h device code for mx29f004b vih vil 0 1 0 0 0 1 1 0 46h chip protection verification x vih 0 0 0 0 0 0 0 1 01h(protected) x vih 0 0 0 0 0 0 0 0 00h(unprotected) table 3. expanded silicon id code
9 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 sector erase commands the automatic sector erase does not require the de- vice to be entirely pre-programmed prior to executing the automatic set-up sector erase command and auto- matic sector erase command. upon executing the au- tomatic sector erase command, the device will auto- matically program and verify the sector(s) memory for an all-zero data pattern. the system is not required to provide any control or timing during these operations. when the sector(s) is automatically verified to contain an all-zero pattern, a self-timed sector erase and verify begin. the erase and verify operations are complete when the data on q7 is "1" and the data on q6 stops toggling for two consecutive read cycles, at which time the device returns to the read mode. the system is not required to provide any control or timing during these operations. when using the automatic sector erase algorithm, note that the erase automatically terminates when adequate erase margin has been achieved for the memory array (no erase verification command is required). sector erase is a six-bus cycle operation. there are two "unlock" write cycles. these are followed by writing the set-up command 80h. two more "unlock" write cycles are then followed by the sector erase command 30h. the sector address is latched on the falling edge of we or ce, whicheven happens later, while the command (data) is latched on the rising edge of we or ce, whicheven happens first. sector addresses selected are loaded into internal register on the sixth falling edge of we or ce, whicheven happens later. each successive sector load cycle started by the falling edge of we or ce, whicheven happens later must begin within 30us from the rising edge of the preceding we or ce, whicheven happens first. otherwise, the loading period ends and internal auto sector erase cycle starts. (monitor q3 to determine if the sector erase timer window is still open, see section q3, sector erase timer.) any command other than sector erase(30h) or erase suspend(b0h) during the time-out period resets the device to read mode. status q7 q6 q5 q3 q2 note1 note2 byte program in auto program algorithm q7 toggle 0 n/a no toggle auto erase algorithm 0 toggle 0 1 toggle erase suspend read 1 no 0 n/a toggle in progress (erase suspended sector) toggle erase suspended mode erase suspend read data data data data data (non-erase suspended sector) erase suspend program q7 toggle 0 n/a n/a byte program in auto program algorithm q7 toggle 1 n/a no toggle exceeded auto erase algorithm 0 toggle 1 1 toggle time limits erase suspend program q7 toggle 1 n/a n/a table 4. write operation status note: 1. q7 and q2 require a valid address when reading status information. refer to the appropriate subsection for further details. 2. q5 switches to '1' when an auto program or auto erase operation has exceeded the maximum timing limits. see "q5:exceeded timing limits " for more information.
10 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 erase suspend this command only has meaning while the state ma- chine is executing automatic sector erase operation, and therefore will only be responded during automatic sector erase operation. when the erase suspend com- mand is written during a sector erase operation, the de- vice requires a maximum of 100us to suspend the erase operations. however, when the erase suspend command is written during the sector erase time-out, the device immediately terminates the time-out period and suspends the erase operation. after this command has been ex- ecuted, the command register will initiate erase suspend mode. the state machine will return to read mode auto- matically after suspend is ready. at this time, state ma- chine only allows the command register to respond to the read memory array, erase resume and program commands. the system can determine the status of the program operation using the q7 or q6 status bits, just as in the standard program operation. after an erase-suspend pro- gram operation is complete, the system can once again read array data within non-suspended sectors. erase resume this command will cause the command register to clear the suspend state and return back to sector erase mode but only if an erase suspend command was previously issued. erase resume will not have any effect in all other conditions. another erase suspend command can be written after the chip has resumed erasing. set-up automatic program commands to initiate automatic program mode, a three-cycle com- mand sequence is required. there are two "unlock" write cycles. these are followed by writing the automatic pro- gram command a0h. once the automatic program command is initiated, the next we or ce pulse causes a transition to an active programming operation. addresses are latched on the falling edge, and data are internally latched on the rising edge of the we or ce, whicheven happens first pulse. the rising edge of we or ce, whicheven hap- pens first also begins the programming operation. the system is not required to provide further controls or tim- ings. the device will automatically provide an adequate internally generated program pulse and verify margin. if the program operation was unsuccessful, the data on q5 is "1"(see table 4), indicating the program operation exceed internal timing limit. the automatic programming operation is completed when the data read on q6 stops toggling for two consecutive read cycles and the data on q7 and q6 are equivalent to data written to these two bits, at which time the device returns to the read mode (no program verify command is required). data polling-q7 the mx29f004t/b also features data polling as a method to indicate to the host system that the auto- matic program or erase algorithms are either in progress or completed. while the automatic programming algorithm is in opera- tion, an attempt to read the device will produce the comple- ment data of the data last written to q7. upon comple- tion of the automatic program algorithm an attempt to read the device will produce the true data last written to q7. the data polling feature is valid after the rising edge of the fourth we or ce, whicheven happens first pulse of the four write pulse sequences for automatic program. while the automatic erase algorithm is in operation, q7 will read "0" until the erase operation is competed. upon completion of the erase operation, the data on q7 will read "1". the data polling feature is valid after the rising edge of the sixth we or ce, whicheven happens first pulse of six write pulse sequences for automatic chip/ sector erase. the data polling feature is active during automatic pro- gram/erase algorithm or sector erase time-out. (see sec- tion q3 sector erase timer)
11 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 q2 toggles when the system reads at addresses within those sectors that have been selected for erasure. (the system may use either oe or ce to control the read cycles.) but q2 cannot distinguish whether the sector is actively erasing or is erase-suspended. q6, by com- parison, indicates whether the device is actively eras- ing, or is in erase suspend, but cannot distinguish which sectors are selected for erasure. thus, both status bits are required for sectors and mode information. refer to table 4 to compare outputs for q2 and q6. reading toggle bits q6/ q2 whenever the system initially begins reading toggle bit status, it must read q7-q0 at least twice in a row to determine whether a toggle bit is toggling. typically, the system would note and store the value of the toggle bit after the first read. after the second read, the system would compare the new value of the toggle bit with the first. if the toggle bit is not toggling, the device has completed the program or erase operation. the system can read array data on q7-q0 on the following read cycle. however, if after the initial two read cycles, the system determines that the toggle bit is still toggling, the sys- tem also should note whether the value of q5 is high (see the section on q5). if it is, the system should then determine again whether the toggle bit is toggling, since the toggle bit may have stopped toggling just as q5 went high. if the toggle bit is no longer toggling, the device has successfully completed the program or erase op- eration. if it is still toggling, the device did not complete the operation successfully, and the system must write the reset command to return to reading array data. the remaining scenario is that system initially determines that the toggle bit is toggling and q5 has not gone high. the system may continue to monitor the toggle bit and q5 through successive read cycles, determining the sta- tus as described in the previous paragraph. alterna- tively, it may choose to perform other system tasks. in this case, the system must start at the beginning of the algorithm when it returns to determine the status of the operation. q6:toggle bit i toggle bit i on q6 indicates whether an automatic pro- gram or erase algorithm is in progress or complete, or whether the device has entered the erase suspend mode. toggle bit i may be read at any address, and is valid after the rising edge of the final we or ce, whicheven happens first pulse in the command sequence (prior to the program or erase operation), and during the sector time-out. during an automatic program or erase algorithm opera- tion, successive read cycles to any address cause q6 to toggle. the system may use either oe or ce to con- trol the read cycles. when the operation is complete, q6 stops toggling. after an erase command sequence is written, if the chip has been protected, q6 toggles and returns to reading array data. the system can use q6 and q2 together to determine whether a sector is actively erasing or is erase sus- pended. when the device is actively erasing (that is, the automatic erase algorithm is in progress), q6 toggling. when the device enters the erase suspend mode, q6 stops toggling. however, the system must also use q2 to determine which sectors are erasing or erase-sus- pended. alternatively, the system can use q7. if a program address falls within a protected sector, q6 toggles for approximately 2us after the program com- mand sequence is written, then returns to reading array data. q6 also toggles during the erase-suspend-program mode, and stops toggling once the automatic program algo- rithm is complete. table 4 shows the outputs for toggle bit i on q6. q2:toggle bit ii the "toggle bit ii" on q2, when used with q6, indicates whether a particular sector is actively erasing (that is, the automatic erase algorithm is in process), or whether that sector is erase-suspended. toggle bit i is valid af- ter the rising edge of the final we or ce, whicheven happens first pulse in the command sequence.
12 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 q5 exceeded timing limits q5 will indicate if the program or erase time has ex- ceeded the specified limits (internal pulse count). under these conditions q5 will produce a "1". this time-out condition indicates that the program or erase cycle was not successfully completed. data polling and toggle bit are the only operating functions of the device under this condition. if this time-out condition occurs during sector erase op- eration, it specifies that a particular sector is bad and it may not be reused. however, other sectors are still func- tional and may be used for the program or erase opera- tion. the device must be reset to use other sectors. write the reset command sequence to the device, and then execute program or erase command sequence. this allows the system to continue to use the other active sectors in the device. if this time-out condition occurs during the chip erase operation, it specifies that the entire chip is bad or com- bination of sectors are bad. if this time-out condition occurs during the byte program- ming operation, it specifies that the entire sector con- taining that byte is bad and this sector may not be re- used, (other sectors are still functional and can be re- used). the time-out condition may also appear if a user tries to program a non blank location without erasing. in this case the device locks out and never completes the au- tomatic algorithm operation. hence, the system never reads a valid data on q7 bit and q6 never stops tog- gling. once the device has exceeded timing limits, the q5 bit will indicate a "1". please note that this is not a device failure condition since the device was incorrectly used. data protection the mx29f004t/b is designed to offer protection against accidental erasure or programming caused by spurious system level signals that may exist during power transi- tion. during power up the device automatically resets the state machine in the read mode. in addition, with its control register architecture, alteration of the memory contents only occurs after successful completion of specific command sequences. the device also incorpo- rates several features to prevent inadvertent write cycles resulting from vcc power-up and power-down transition or system noise. q3 sector erase timer after the completion of the initial sector erase command sequence, the sector erase time-out will begin. q3 will remain low until the time-out is complete. data polling and toggle bit are valid after the initial sector erase com- mand sequence. if data polling or the toggle bit indicates the device has been written with a valid erase command, q3 may be used to determine if the sector erase timer window is still open. if q3 is high ("1") the internally controlled erase cycle has begun; attempts to write subsequent commands to the device will be ignored until the erase operation is completed as indicated by data polling or toggle bit. if q3 is low ("0"), the device will accept addi- tional sector erase commands. to insure the command has been accepted, the system software should check the status of q3 prior to and following each subsequent sector erase command. if q3 were high on the second status check, the command may not have been accepted. write pulse "glitch" protection noise pulses of less than 5ns(typical) on ce or we will not initiate a write cycle. logical inhibit writing is inhibited by holding any one of oe = vil, ce = vih or we = vih. to initiate a write cycle ce and we must be a logical zero while oe is a logical one. power supply decoupling in order to reduce power switching effect, each device should have a 0.1uf ceramic capacitor connected be- tween its vcc and gnd.
13 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 chip protection with 12v system the mx29f004t/b features chip protection, which will disable both program and erase operations. to activate this mode, the programming equipment must force vid on address pin a9 and control pin oe, (suggest vid=12v) a6=vil and ce=vil.(see table 2) programming of the protection circuitry begins on the falling edge of the we or ce, whicheven happens later pulse and is terminated on the rising edge. please refer to chip protect algo- rithm and waveform. to verify programming of the protection circuitry, the pro- gramming equipment must force vid on address pin a9 ( with ce and oe at vil and we at vih). when a1=1, it will produce a logical "1" code at device output q0 for the protected status. otherwise the device will produce 00h for the unprotected status. in this mode, the ad- dresses, except for a1, are don't care. address loca- tions with a1 = vil are reserved to read manufacturer and device codes. (read silicon id) it is also possible to determine if chip is protected in the system by writing a read silicon id command. per- forming a read operation with a1=vih, it will produce a logical "1" at q0 for the protected status. chip unprotect with 12v system the mx29f004t/b also features the chip unprotect mode, so that all sectors are unprotected after chip unprotect is completed to incorporate any changes in the code. to activate this mode, the programming equipment must force vid on control pin oe and address pin a9. the ce pins must be set at vil. pins a6 must be set to vih. (see table 2) refer to chip unprotect algorithm and waveform for the chip unprotect algorithm. the unprotection mechanism begins on the falling edge of the we or ce, whicheven happens later pulse and is terminated on the rising edge. it is also possible to determine if the chip is unprotected in the system by writing the read silicon id command. performing a read operation with a1=vih, it will produce 00h at data outputs(q0-q7) for an unprotected sector. it is noted that all sectors are unprotected after the chip unprotect algorithm is completed. power-up sequence the mx29f004t/b powers up in the read only mode. in addition, the memory contents may only be altered after successful completion of the predefined command se- quences. chip protection without 12v system the mx29f004t/b also feature a chip protection method in a system without 12v power supply. the programming equipment do not need to supply 12 volts to protect all sectors. the details are shown in chip protect algorithm and waveform. chip unprotect without 12v system the mx29f004t/b also feature a chip unprotection method in a system without 12v power supply. the pro- gramming equipment do not need to supply 12 volts to unprotect all sectors. the details are shown in chip unprotect algorithm and waveform.
14 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 29f004t/b-55 29f004t/b-70 29f004t/b-90 29f004t/b-12 symbol parameter min. max. min. max. min. max. min. max. unit conditions tacc address to output delay 55 70 90 120 ns ce=oe=vil tce ce to output delay 55 70 90 120 ns oe=vil toe oe to output delay 40 40 40 50 ns ce=vil tdf oe high to output float 0 30 0 30 0 40 0 40 ns ce=vil (note 1) toh address to output hold 0 0 0 0 ns ce=oe=vil note: 1. tdf is defined as the time at which the output achieves the open circuit condition and data is no longer driven. test conditions: ? input pulse levels: 0.45v/2.4v ? input rise and fall times is equal to or less than 10ns ? output load: 1 ttl gate + 100pf (including scope and jig) ? reference levels for measuring timing: 0.8v, 2.0v notes: 1. vil min. = -1.0v for pulse width is equal to or less than 50 ns. vil min. = -2.0v for pulse width is equal to or less than 20 ns. 2. vih max. = vcc + 1.5v for pulse width is equal to or less than 20 ns. if vih is over the specified maximum value, read operation cannot be guaranteed. read operation dc characteristics (ta = -40 c to 85 c, vcc = 5v 10%) symbol parameter min. typ max. unit conditions ili input leakage current 1 ua vin = gnd to vcc ilo output leakage current 10 ua vout = gnd to vcc isb1 standby vcc current 1 ma ce = vih isb2 1 5 ua ce = vcc + 0.3v icc1 operating vcc current 30 ma iout = 0ma, f=5mhz icc2 50 ma iout = 0ma, f=10mhz vil input low voltage -0.3 (note 1) 0.8 v vih input high voltage 2.0 vcc + 0.3 v vol output low voltage 0.45 v iol = 2.1ma voh1 output high voltage(ttl) 2.4 v ioh = -2ma voh2 output high voltage(cmos) vcc-0.4 v ioh = -100ua,vcc=vcc min capacitance (ta = 25 o c, f = 1.0 mhz) symbol parameter min. typ max. unit conditions cin1 input capacitance 8 pf vin = 0v cin2 control pin capacitance 12 pf vin = 0v cout output capacitance 12 pf vout = 0v ac characteristics (ta = -40 o c to 85 o c, vcc = 5v 10%)
15 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 absolute maximum ratings rating value ambient operating temperature -40 o c to 85 o c storage temperature -65 o c to 125 o c applied input voltage -0.5v to 7.0v applied output voltage -0.5v to 7.0v vcc to ground potential -0.5v to 7.0v a9 & oe -0.5v to 13.5v notice: stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. notice: specifications contained within the following tables are subject to change. read timing waveforms addresses ce oe tacc we vih vil vih vil vih vil vih vil voh vol high z high z data valid toe tdf tce outputs toh add valid notes: 1. vil min. = -0.6v for pulse width is equal to or less than 20ns. 2. if vih is over the specified maximum value, programming operation cannot be guranteed. 3. icces is specified with the device de-selected. if the device is read during erase suspend mode, current draw is the sum of icces and icc1 or icc2. 4. all current are in rms unless otherwise noted. dc characteristics (ta = -40 o c to 85 o c, vcc = 5v 10%) symbol parameter min. typ max. unit conditions icc1 (read) operating vcc current 30 ma iout=0ma, f=5mhz icc2 50 ma iout=0ma, f=10mhz icc3 (program) 50 ma in programming icc4 (erase) 50 ma in erase icces vcc erase suspend current 2 ma ce=vih, erase suspended command programming/data programming/erase operation
16 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 ac characteristics ta = -40 o c to 85 o c, vcc = 5v 10% 29f004t/b-55 29f004t/b-70 29f004t/b-90 29f004t/b-12 symbol parameter min. max. min. max. min. max. min. max. unit toes oe setup time 50 50 50 50 ns tcwc command programming cycle 55 70 90 120 ns tcep we programming pulse width 45 45 45 50 ns tceph1 we programming pulse width high 20 20 20 20 ns tceph2 we programming pulse width high 20 20 20 20 ns tas address setup time 0 0 0 0 ns tah address hold time 45 45 45 50 ns tds data setup time 30 30 45 50 ns tdh data hold time 0 0 0 0 ns tcesc ce setup time before command write 0 0 0 0 ns tdf output disable time (note 1) 30 30 40 40 ns taetc total erase time in auto chip erase 4(typ.) 32 4(typ.) 32 4(typ.) 32 4(typ.) 32 s taetb total erase time in auto sector erase 1.3(typ.) 10.4 1.3(typ.) 10.4 1.3(typ.) 10.4 1.3(typ.) 10.4 s tavt total programming time in auto verify 7 210 7 210 7 210 7 210 us tbal sector address load time 100 100 100 100 us tch ce hold time 0 0 0 0 ns tcs ce setup to we going low 0 0 0 0 ns tvlht voltage transition time 4 4 4 4 us toesp oe setup time to we active 4 4 4 4 us twpp1 write pulse width for chip protect 10 10 10 10 us twpp2 write pulse width for chip unprotect 12 12 12 12 ms notes: 1. tdf defined as the time at which the output achieves the open circuit condition and data is no longer driven.
17 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 switching test circuits switching test waveforms command write timing waveform 2.0v 2.0v 0.8v 0.8v test points 2.4v 0.45v ac testing: inputs are driven at 2.4v for a logic "1" and 0.45v for a logic "0". input pulse rise and fall times are <20ns. output input addresses ce oe we din tds tah data tdh tcs tch tcwc tceph1 tcep toes tas vcc 5v vih vil vih vil vih vil vih vil vih vil add valid device under test diodes=in3064 or equivalent cl 1.2k ohm 1.6k ohm +5v cl=100pf including jig capacitance
18 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 one byte data is programmed. verify in fast algorithm and additional programming by external control are not required because these operations are executed auto- matically by internal control circuit. programming completion can be verified by data polling and toggle bit checking after automatic verification starts. device outputs data during programming and data after pro- gramming on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic programming timing waveform tcwc tas tcep tds tdh tdf vcc 5v ce oe q0,q1,q2 q4(note 1) we a11~a18 tceph1 tah add valid tcesc q7 command in add valid a0~a10 command in command in command in data in data in data command in command in data data tavt toe data polling 2aah 555h 555h (q0~q7) command #55h command #a0h notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit command #aah automatic programming timing waveform
19 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes no toggle bit checking q6 not toggled verify byte ok yes q5 = 1 reset auto program completed auto program exceed timing limit no invalid command yes no .
20 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 all data in chip are erased. external erase verification is not required because data is erased automatically by internal control circuit. erasure completion can be verified by data polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic chip erase timing waveform automatic chip erase timing waveform tcwc tas tcep tds tdh vcc 5v ce oe q0,q1, q4(note 1) we a11~a18 tceph1 tah q7 command in a0~a10 command in command in command in command in command in taetc data polling 2aah 555h 555h command #aah command #55h command #80h (q0~q7) notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2: toggle bit 555h 2aah 555h command in command in command #aah command in command in command #55h command in command in command #10h
21 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 10h address 555h write data 55h address 2aah reset auto chip erase exceed timing limit data polling q7 = 1 yes q5 = 1 auto chip erase completed no . no invalid command yes
22 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 sector data indicated by a13 to a18 are erased. external erase verify is not required because data are erased automatically by internal control circuit. erasure comple- tion can be verified by data polling and toggle bit checking after automatic erase starts. device outputs 0 during erasure and 1 after erasure on q7.(q6 is for toggle bit; see toggle bit, data polling, timing waveform) automatic sector erase timing waveform automatic sector erase timing waveform tah sector address0 555h 2aah 2aah 555h 555h sector address1 sector addressn vcc 5v ce oe q0,q1, q4(note 1) we a13~a18 q7 a0~a10 command in command in command in command in command in command in command in command in command in command in command in command in command in command in command #30h command #30h command #30h command #55h command #aah command #80h command #55h command #aah (q0~q7) command in command in tdh tds tcep tcwc taetb tbal data polling tceph1 tas notes: (1). q6:toggle bit, q5:timing-limit bit, q3: time-out bit, q2: toggle bit
23 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no toggle bit checking q6 not toggled write data 30h sector address write data 55h address 2aah reset auto sector erase exceed timing limit data polling q7 = 1 q5 = 1 auto sector erase completed load other sector addrss if necessary (load other sector address) yes no last sector to erase time-out bit checking q3=1 ? toggle bit checking q6 toggled ? invalid command no yes yes no yes no
24 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 erase suspend/erase resume flowchart start write data b0h toggle bit checking q6 not toggled yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no
25 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 timing waveform for chip protection for system with 12v toe data oe we 12v 5v 12v 5v ce a9 a1 a6 toesp twpp 1 tvlht tvlht tvlht verify 01h f0h
26 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 timing waveform for chip unprotection for system with 12v toe data oe we 12v 5v 12v 5v ce a9 a1 toesp twpp 2 tvlht tvlht tvlht verify 00h a6 f0h
27 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 chip protection algorithm for system with 12v start plscnt=1 chip protection complete data=01h? ye s oe=vid,a9=vid,ce=vil a6=vil activate we pulse time out 10us set we=vih, ce=oe=vil a9 should remain vid read data with a1=1 remove vid from a9 write reset command device failed plscnt=32? ye s no no
28 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 timing waveform for chip protection for system without 12v toe data oe we ce a1 a6 * see the following note! verify 01h 5v note: 1. must issue "unlock for sector protect/unprotect" command before chip protection for a system without 12v provided. 2. except f0h toggle bit polling don't care (note 2) tcep f0h
29 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 timing waveform for chip unprotection for system without 12v toe data we ce a1 verify 00h a6 note: 1. must issue "unlock for sector protect/unprotect" command before chip unprotection for a system without 12v provided. 2. except f0h oe tcep 5v toggle bit polling don't care (note 2) * see the following note! f0h
30 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 chip protection algorithm for system without 12v start plscnt=1 chip protection complete data=01h? activate we pulse to start data don't care set ce=oe=vil a9=vih read data from chip, a1=1 write reset command device failed plscnt=32? ye s no increment plscnt no write "unlock for chip protect/unprotect" command(table1) oe=vih, a9=vih ce=vil, a6=vil toggle bit checking q6 not toggled no . ye s
31 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 chip unprotection algorithm for system without 12v start plscnt=1 chip unprotect complete toggle bit checking q6 not toggled ye s write "unlock for chip protect/unprotect" command (table 1) set oe=a9=vih ce=vil, a6=1 set oe=ce=vil, a9=vih, a1=1 active we pulse to start data don't care data=00h? read data from device write reset command device failed plscnt=1000? no increment plscnt no ye s ye s no
32 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 id code read timing waveform tacc tce tacc toe toh toh tdf data out c2h 45h/46h vid vih vil add a9 add a2-a8 a10-a18 ce a1 oe we add a0 data out data q0-q7 vcc 5v vih vil vih vil vih vil vih vil vih vil vih vil vih vil
33 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 ordering information plastic package (top boot sector as an example, for bottom boot sector ones, mx29f004txx will be changed to mx29f004bxx) part no. access operating current standby current package time (ns) max.(ma) max.(ua) mx29f004tqc-55 55 30 5 32 pin plcc mx29f004tqc-70 70 30 5 32 pin plcc mx29f004tqc-90 90 30 5 32 pin plcc mx29f004tqc-12 120 30 5 32 pin plcc mx29f004ttc-55 55 30 5 32 pin tsop (normal type) mx29f004ttc-70 70 30 5 32 pin tsop (normal type) mx29f004ttc-90 90 30 5 32 pin tsop (normal type) mx29f004ttc-12 120 30 5 32 pin tsop (normal type) mx29f004tpc-55 55 30 5 32 pin pdip mx29f004tpc-70 70 30 5 32 pin pdip mx29f004tpc-90 90 30 5 32 pin pdip mx29f004tpc-12 120 30 5 32 pin pdip mx29f004tqi-55 55 30 5 32 pin plcc mx29f004tqi-70 70 30 5 32 pin plcc mx29f004tqi-90 90 30 5 32 pin plcc mx29f004tqi-12 120 30 5 32 pin plcc mx29f004tti-55 55 30 5 32 pin tsop (normal type) mx29f004tti-70 70 30 5 32 pin tsop (normal type) mx29f004tti-90 90 30 5 32 pin tsop (normal type) mx29f004tti-12 120 30 5 32 pin tsop (normal type) mx29f004tpi-55 55 30 5 32 pin pdip mx29f004tpi-70 70 30 5 32 pin pdip mx29f004tpi-90 90 30 5 32 pin pdip mx29f004tpi-12 120 30 5 32 pin pdip
34 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 min. max. input voltage with respect to gnd on all pins except i/o pins -1.0v 13.5v input voltage with respect to gnd on all i/o pins -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 5.0v, one pin at a time. limits parameter min. typ.(2) max.(3) units sector erase time 1.3 10.4 sec chip erase time 4 32 sec byte programming time 7 210 us chip programming time 4 12 sec erase/program cycles 100,000 cycles latch-up characteristics erase and programming performance (1) note: 1. not 100% tested, excludes external system level over head. 2. typical values measured at 25 c,5v. 3. maximum values measured at 25 c,4.5v. parameter min. unit data retention time 20 years data retention
35 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 package information 32-pin plastic dip
36 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 32-pin plastic leaded chip carrier (plcc)
37 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 32-pin plastic tsop
38 mx29f004t/b p/n:pm0554 rev. 1.6, jul. 18, 2002 revision history revision description page date 1.0 to remove "advanced information" data sheet marking and p1 jul/01/1999 contain information on products in full production. 1.1 to improve icc1 spec:from 40ma @5mhz to 30ma @5mhz p1,14,15,33 jul/12/1999 1.2 1. program/erase cycle times:10k cycles-->100k cycles p1,34 dec/20/1999 2. to add data retention minimum 20 years p1,34 3. to modify timing of sector address loading period while p9 operating multi-sector erase from 80us to 30us 4. to modify tbal from 80us to 100us p16 5. to remove a9 from "timing waveform for sector protection for p28 system without 12v" to remove a9 from "timing waveform for chip unprotection for p29 system without 12v" 1.3 add erase suspend ready max. 100us in erase suspend's p10 ma y/30/2000 section at page 10 1.4 to modify "package information" p35~37 jun/12/2001 1.5 1. to corrected typing error all jul/01/2002 1.6 1. add 55ns speed option p14,16,33 jul/18/2002 2. add industrial grade level p14,15,16,33
mx29f004t/b m acronix i nternational c o., l td. headquarters: tel:+886-3-578-6688 fax:+886-3-563-2888 europe office: tel:+32-2-456-8020 fax:+32-2-456-8021 japan office: tel:+81-44-246-9100 fax:+81-44-246-9105 singapore office: tel:+65-348-8385 fax:+65-348-8096 taipei office: tel:+886-2-2509-3300 fax:+886-2-2509-2200 m acronix a merica, i nc. tel:+1-408-453-8088 fax:+1-408-453-8488 chicago office: tel:+1-847-963-1900 fax:+1-847-963-1909 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifications without notice.

▲Up To Search▲

Price & Availability of MX29F004BQI-70

	To Download MX29F004BQI-70 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .